High performance system-on-chip passive device using post passivation process

ABSTRACT

A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

RELATED PATENT APPLICATIONS

This application is related to, Ser. No. 10/445,558, filed on May 27, 2003, and assigned to a common assignee.

This application is related to, Ser. No. 10/445,560, filed on May 27, 2003, and assigned to a common assignee.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the manufacturing of high performance Integrated Circuit (IC's), and, more specifically, to methods of creating high performance electrical components (such as an inductor) on the surface of a semiconductor substrate by reducing the electromagnetic losses that are typically incurred in the surface of the substrate.

(2) Description of the Related Art

The continued emphasis in the semiconductor technology is to create improved performance semiconductor devices at competitive prices. This emphasis over the years has resulted in extreme miniaturization of semiconductor devices, made possible by continued advances of semiconductor processes and materials in combination with new and sophisticated device designs. Most of the semiconductor devices that are at this time being created are aimed at processing digital data. There are however also numerous semiconductor designs that are aimed at incorporating analog functions into devices that simultaneously process digital and analog data, or devices that can be used for the processing of only analog data. One of the major challenges in the creation of analog processing circuitry (using digital processing procedures and equipment) is that a number of the components that are used for analog circuitry are large in size and are therefore not readily integrated into devices that typically have feature sizes that approach the sub-micron range. The main components that offer a challenge in this respect are capacitors and inductors, since both these components are, for typical analog processing circuits, of considerable size.

A typical application for inductors of the invention is in the field of modern mobile communication applications. One of the main applications of semiconductor devices in the field of mobile communication is the creation of Radio Frequency (RF) amplifiers. RF amplifiers contain a number of standard components, a major component of a typical RF amplifier is a tuned circuit that contains inductive and capacitive components. Tuned circuits form, dependent on and determined by the values of their inductive and capacitive components, an impedance that is frequency dependent, enabling the tuned circuit to either present a high or a low impedance for signals of a certain frequency. The tuned circuit can therefore either reject or pass and further amplify components of an analog signal, based on the frequency of that component. The tuned circuit can in this manner be used as a filter to filter out or remove signals of certain frequencies or to remove noise from a circuit configuration that is aimed at processing analog signals. The tuned circuit can also be used to form a high electrical impedance by using the LC resonance of the circuit and to thereby counteract the effects of parasitic capacitances that are part of a circuit. One of the problems that is encountered when creating an inductor on the surface of a semiconductor substrate is that the self-resonance that is caused by the parasitic capacitance between the (spiral) inductor and the underlying substrate will limit the use of the inductor at high frequencies. As part of the design of such an inductor it is therefore of importance to reduce the capacitive coupling between the created inductor and the underlying substrate.

At high frequencies, the electromagnetic field that is generated by the inductor induces eddy currents in the underlying silicon substrate. Since the silicon substrate is a resistive conductor, the eddy currents will consume electromagnetic energy resulting in significant energy loss, resulting in a low Q inductor. This is one of the main reasons for a low Q value of a inductor, whereby the resonant frequency of 1/√(LC) limits the upper boundary of the frequency. In addition, the eddy currents that are induced by the inductor will interfere with the performance of circuitry that is in close physical proximity to the inductor. Furthermore, the fine metal lines used to form the inductor also consume energy, due to the metal's resistance, and result in low Q inductors.

It has already been pointed out that one of the key components used in creating high frequency analog semiconductor devices is the inductor that forms part of an LC resonance circuit. In view of the high device density that is typically encountered in semiconductor devices and the subsequent intense use of the substrate surface area, the creation of the inductor must incorporate the minimization of the surface area that is required for the inductor, while at the same time maintaining a high Q value for the inductor. Typically, inductors that are created on the surface of a substrate are of a spiral shape whereby the spiral is created in a plane that is parallel with the plane of the surface of the substrate. Conventional methods that are used to create the inductor on the surface of a substrate suffer several limitations. Most high Q inductors form part of a hybrid device configuration or of Monolithic Microwave Integrated Circuits (MMIC's) or are created as discrete components, the creation of which is not readily integratable into a typical process of Integrated Circuit manufacturing. It is clear that, by combining the creation on one semiconductor monolithic substrate of circuitry that is aimed at the functions of analog data manipulation and analog data storage with the functions of digital data manipulation and digital data storage, a number of significant advantages can be achieved. Such advantages include the reduction of manufacturing costs and the reduction of power consumption by the combined functions. The spiral form of the inductor that is created on the surface of a semiconductor substrate however results, due to the physical size of the inductor, in parasitic capacitances between the inductor wiring and the underlying substrate and causes electromagnetic energy losses in the underlying resistive silicon substrate. These parasitic capacitances have a serious negative effect on the functionality of the created LC circuit by sharply reducing the frequency of resonance of the tuned circuit of the application.

More seriously, the inductor-generated electromagnetic field will induce eddy currents in the underlying resistive silicon substrate, causing a significant energy loss that results in low Q inductors.

The performance parameter of an inductor is typically indicated is the Quality (Q) factor of the inductor. The quality factor Q of an inductor is defined as Q=Es/El, wherein Es is the energy that is stored in the reactive portion of the component while El is the energy that is lost in the reactive portion of the component. The higher the quality of the component, the closer the resistive value of the component approaches zero while the Q factor of the component approaches infinity. For inductors that are created overlying a silicon substrate, the electromagnetic energy that is created by the inductor will primarily be lost in the resistive silicon of the underlying substrate and in the metal lines that are created to form the inductor. For components, the quality factor serves as a measure of the purity of the reactance (or the susceptance) of the component, which can be degraded due to the resistive silicon substrate, the resistance of the metal lines and dielectric losses. In an actual configuration, there are always some physical resistors that will dissipate power, thereby decreasing the power that can be recovered. The quality factor Q is dimensionless. A Q value of greater than 100 is considered very high for discrete inductors that are mounted on the surface of Printed Circuit Boards. For inductors that form part of an integrated circuit, the Q value is typically in the range between about 3 and 10.

In creating an inductor on a monolithic substrate on which additional semiconductor devices are created, the parasitic capacitances that occur as part of this creation limit the upper bound of the cut-off frequency that can be achieved for the inductor using conventional silicon processes. This limitation is, for many applications, not acceptable. Dependent on the frequency at which the LC circuit is designed to resonate, significantly larger values of quality factor, such as for instance 50 or more, must be available. Prior Art has in this been limited to creating values of higher quality factors as separate units, and in integrating these separate units with the surrounding device functions. This negates the advantages that can be obtained when using the monolithic construction of creating both the inductor and the surrounding devices on one and the same semiconductor substrate. The non-monolithic approach also has the disadvantage that additional wiring is required to interconnect the sub-components of the assembly, thereby again introducing additional parasitic capacitances and resistive losses over the interconnecting wiring network. For many of the applications of a RF amplifier, such as portable battery powered applications, power consumption is at a premium and must therefore be as low as possible. By raising the power consumption, the effects of parasitic capacitances and resistive power loss can be partially compensated, but there are limitations to even this approach. These problems take on even greater urgency with the rapid expansion of wireless applications, such as portable telephones and the like. Wireless communication is a rapidly expanding market, where the integration of RF integrated circuits is one of the most important challenges. One of the approaches is to significantly increase the frequency of operation to for instance the range of 10 to 100 GHz. For such high frequencies, the value of the quality factor obtained from silicon-based inductors is significantly degraded. For applications in this frequency range, monolithic inductors have been researched using other than silicon as the base for the creation of the inductors. Such monolithic inductors have for instance been created using sapphire or GaAs as a base. These inductors have considerably lower substrate losses than their silicon counterparts (no eddy current, hence no loss of electromagnetic energy) and therefore provide much higher Q inductors. Furthermore, they have lower parasitic capacitance and therefore provide higher frequency operation capabilities. Where however more complex applications are required, the need still exists to create inductors using silicon as a substrate. For those applications, the approach of using a base material other than silicon has proven to be too cumbersome while for instance GaAs as a medium for the creation of semiconductor devices is as yet a technical challenge that needs to be addressed. It is known that GaAs is a semi-insulating material at high frequencies, reducing the electromagnetic losses that are incurred in the surface of the GaAs substrate, thereby increasing the Q value of the inductor created on the GaAs surface. GaAs RF chips however are expensive, a process that can avoid the use of GaAs RF chips therefore offers the benefit of cost advantage.

A number of different approaches have been used to incorporate inductors into a semiconductor environment without sacrificing device performance due to substrate losses. One of these approaches has been to selectively remove (by etching) the silicon underneath the inductor (using methods of micro machining), thereby removing substrate resistive energy losses and parasitic effects. Another method has been to use multiple layers of metal (such as aluminum) interconnects or of copper damascene interconnects.

Other approaches have used a high resistivity silicon substrate thereby reducing resistive losses in the silicon substrate. Resistive substrate losses in the surface of the underlying substrate form a dominant factor in determining the Q value of silicon inductors. Further, biased wells have been proposed underneath a spiral conductor, this again aimed at reducing inductive losses in the surface of the substrate. A more complex approach has been to create an active inductive component that simulates the electrical properties of an inductor as it is applied in active circuitry. This latter approach however results in high power consumption by the simulated inductor and in noise performance that is unacceptable for low power, high frequency applications. All of these approaches have as common objectives to enhance the quality (Q) value of the inductor and to reduce the surface area that is required for the creation of the inductor. The most important consideration in this respect is the electromagnetic energy losses due to the electromagnetic induced eddy currents in the silicon substrate.

When the dimensions of Integrated Circuits are scaled down, the cost per die is decreased while some aspects of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.

Current techniques for building an inductor on the surface of a semiconductor substrate use fine-line techniques whereby the inductor is created under a layer of passivation. This however implies close physical proximity between the created inductor and the surface of the substrate over which the inductor has been created (typically less than 10 μm), resulting in high electro-magnetic losses in the silicon substrate which in turn results in reducing the Q value of the inductor.

U.S. Pat. No. 5,212,403 (Nakanishi) shows a method of forming wiring connections both inside and outside (in a wiring substrate over the chip) for a logic circuit depending on the length of the wire connections.

U.S. Pat. No. 5,501,006 (Gehman, Jr. et al .) shows a structure with an insulating layer between the integrated circuit (IC) and the wiring substrate. A distribution lead connects the bonding pads of the IC to the bonding pads of the substrate.

U.S. Pat. No. 5,055,907 (Jacobs) discloses an extended integration semiconductor structure that allows manufacturers to integrate circuitry beyond the chip boundaries by forming a thin film multi-layer wiring decal on the support substrate and over the chip. However, this reference differs from the invention.

U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layer interconnect structure of alternating polyimide (dielectric) and metal layers over an IC in a TAB structure.

U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method for reducing RC delay by a PBGA that separates multiple metal layers.

U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate that reduces RC delay by separating the power and I/O traces.

U.S. Pat. No. 6,008,102 (Alford et al.) shows a helix inductor using two metal layers connected by vias.

U.S. Pat. No. 5,372,967 (Sundaram et al.) discloses a helix inductor.

U.S. Pat. No. 5,576,680 (Ling) and U.S. Pat. No. 5,884,990 (Burghartz et al.) show other helix inductor designs.

SUMMARY OF THE INVENTION

It is the primary objective of the invention to improve the RF performance of High Performance Integrated Circuits.

Another objective of the invention is to provide a method for the creation of a high-Q inductor.

Another objective of the invention is to replace the GaAs chip with a silicon chip as a base on which a high-Q inductor is created.

Yet another objective of the invention is to extend the frequency range of the inductor that is created on the surface of a silicon substrate.

It is yet another objective of the invention to create high quality passive electrical components overlying the surface of a silicon substrate.

The above referenced U.S. Pat. No. 6,383,916 adds, in a post passivation processing sequence, a thick layer of dielectric over a layer of passivation and layers of wide and thick metal lines on top of the thick layer of dielectric. The present invention extends referenced U.S. Pat. No. 6,383,916 by in addition creating high quality electrical components, such as an inductor, a capacitor or a resistor, on a layer of passivation or on the surface of a thick layer of dielectric. In addition, the process of the invention provides a method for mounting discrete passive electrical components on the surface of Integrated Circuit chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional representation of the interconnection scheme shown in U.S. Pat. No. 6,383,916.

FIG. 2 is a cross sectional representation of an inductor of the invention, created on a thick layer of polyimide.

FIG. 3 is a top view of an inductor created following the process of the invention.

FIG. 4 is a cross sectional representation of a substrate and overlying layers, an inductor has been created on the surface of a thick layer of polyimide, a layer of conductive material has been added to further insulate the inductor from the underlying silicon substrate.

FIG. 5 a shows an inductor of the invention above a layer of passivation.

FIGS. 5 b-5 c are a cross-sectional representation, and top view, respectively, of inductors of the invention formed on an isolated section of polymer.

FIG. 6 a is a cross sectional representation of a transformer according to the invention, formed over a polymer layer, over a layer of passivation.

FIG. 6 b is a cross sectional representation of a transformer according to the invention, with the bottom coil formed on a layer of passivation.

FIG. 6 c is a three dimensional view of another embodiment of a solenoidal inductor of the invention, over a passivation layer.

FIG. 6 d is a three-dimensional view of a solenoidal inductor of the invention, formed over a polymer layer, over a passivation layer.

FIG. 6 e is a top view of the inductors of FIGS. 6 c and 6 d.

FIG. 6 f is a cross sectional representation of the structure of FIG. 6 e, taken along the line 6 f-6 f′ of FIG. 6 e.

FIG. 6 g is a three dimensional view of an inductor of the invention, in the shape of a toroid.

FIG. 6 h is a top view of the toroidal inductor of FIG. 6 g.

FIGS. 7 a-7 c is a cross sectional representation of a capacitor of the invention, formed over a polymer layer over passivation.

FIG. 8 is a cross sectional representation of a resistor of the invention, formed over a passivation layer.

FIGS. 9 a-9 b are cross sectional representations of a resistor of the invention, formed over a thick polymer layer, over a passivation layer.

FIG. 10 is a cross sectional representation of, a silicon substrate over which a discrete electrical component has been mounted, on the top of a thick polymer layer, using surface mount technology.

FIG. 11 is a cross sectional representation of a silicon substrate, having a passivation layer on the surface of which a discrete electrical component has been mounted, using surface mount technology.

FIGS. 12-18 depict, in cross-sectional form, the creation of gold metal structures of the invention, through a layer of polymer.

FIGS. 19-23 depict the creation of copper metal structures of the invention, through a layer of polymer.

FIGS. 24 a-24 c show alternate methods of connecting to the inductor of the invention.

FIGS. 25 and 26 show extended methods of connecting a capacitor and a resistor under the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

U.S. Pat. No. 6,383,916, assigned to a common assignee as the current invention, teaches an Integrated Circuit structure where re-distribution and interconnect metal layers are created in layers of dielectric over the passivation layer of a conventional Integrated Circuit (IC). A layer of passivation is deposited over the IC, a thick layer of polymer is alternately deposited over the surface of the layer of passivation, and thick, wide metal lines are formed over the passivation.

U.S. Pat. No. 6,303,423, also assigned to a common assignee as the current invention, addresses, among other objectives, the creation of an inductor whereby the emphasis is on creating an inductor of high Q value above the passivation layer of a semiconductor substrate. The high quality of the inductor of the invention allows for the use of this inductor in high frequency applications while incurring minimum loss of power. The invention further addresses the creation of a capacitor and a resistor on the surface of a silicon substrate whereby the main objective (of the process of creating a capacitor and resistor) is to reduce parasitics that are typically incurred by these components in the underlying silicon substrate.

Referring now more specifically to FIG. 1, there is shown a cross section of one implementation of U.S. Pat. No. 6,383,916. The surface of silicon substrate 10 has been provided with transistors 11 and other devices (not shown in FIG. 1). The surface of substrate 10 is covered by a interlevel dielectric (ILD) layer 12, formed over the devices.

Layers 14 represent metal and dielectric layers that are typically created over ILD 12. Layers 14 contain one or more layers of dielectric, interspersed with one or more metal interconnect lines 13 that make up a network of electrical connections. At a top metal layer are points 16 of electrical contact. These points 16 of electrical contact can establish electrical interconnects to the transistors and other devices 11 that have been provided in and on the surface of the substrate 10. A passivation layer 18, formed of, for example, a composite layer of silicon oxide and silicon nitride, is deposited over the surface of layers 14, and function to prevent the penetration of mobile ions (such as sodium ions), moisture, transition metal (such as gold, copper, silver), and other contamination. The passivation layer is used to protect the underlying devices (such as transistors, polysilicon resistors, poly-to-poly capacitors, etc.) and the fine-line metal interconnection.

The key steps of U.S. Pat. No. 6,383,916, begin with the deposition of a thick layer 20 of polyimide that is deposited over the surface of passivation layer 18. Access must be provided to points of electrical contact 16, for this reason a pattern of openings 22, 36 and 38 is formed through the polyimide layer 20 and the passivation layer 18, the pattern of openings 22, 36 and 38 aligns with the pattern of electrical contact points 16. Contact points 16 are, by means of the openings 22/36/38 that are created in the layer 20 of polyimide, electrically extended to the surface of layer 20.

Layer 20 is a polymer, and is preferably polyimide. Polymer 20 may optionally be photosensitive. Examples of other polymers that can be used include benzocyclobutene (BCB), parylene or epoxy-based material such as photoepoxy SU-8 (available from Sotec Microsystems, Renens, Switzerland).

After formation of openings 22/36/38, metallization is performed to create patterned wide metal layers 26 and 28, and to connect to contact points 16. Lines 26 and 28 can be of any design in width and thickness to accommodate specific circuit design requirements, which can be used for power distribution, or as a ground or signal bus. Furthermore, metal 26 may be connected off-chip through wire bonds or solder bumps.

Contact points 16 are located on top of a thin dielectric (layers 14, FIG. 1), and the pad size must be kept small to minimize capacitance with underlying metal layers. In addition, a large pad size will interfere with the routing capability of the layer of metal.

Layer 20 is a thick polymer dielectric layer (for example, polyimide) having a thickness in excess of 2 μm (after curing). The range of the polymer thickness can vary from 2 μm to 150 μm, dependent on electrical design requirements. For a thicker layer of polyimide, the polyimide film can be multiple coated and cured.

U.S. Pat. No. 6,383,916 B1 allows for the interconnection of circuit elements at various distances, over the path 30/32/34 shown in FIG. 1, using the thick, wide (as compared to the underlying “fine line” metallization in layers 14) metal of 28. Thick, wide metal 28 has smaller resistance and capacitance than the fine line metal 14 and is also easier and more cost effective to manufacture.

FIG. 2 shows how the interconnect aspect of U.S. Pat. No. 6,383,916, can be modified to form an inductor on the surface of the thick layer 20 of polyimide. The inductor is created in a plane that is parallel with the surface of the substrate 10 whereby this plane however is separated from the surface of the substrate 10 by the combined heights of layers 12, 14, 18, and 20. FIG. 2 shows a cross section 40 of the inductor taken in a plane that is perpendicular to the surface of substrate 10. The wide and thick metal will also contribute to a reduction of the resistive energy losses. Furthermore, the low resistivity metal, such as gold, silver and copper, can be applied using electroplating, the thickness can be about 20 μm.

By increasing the distance between the inductor and the semiconductor surface, as compared to prior art approaches in which the inductor is formed under the passivation, the electromagnetic field in the silicon substrate will be reduced as the distance is increased, and the Q value of the inductor can be increased. The inductor overlies the layer of passivation and by, in addition, creating the inductor on the surface of a thick layer of dielectric (such as a polymer) formed over the passivation layer. In addition, by using wide and thick metal for the creation of the inductor, the parasitic resistance is reduced.

In an important feature of the invention, the openings 19 in passivation layer 18 may be as small as 0.1 μm wide. Thus, contact pads 16 may also be nearly as small, which allows for greater routing capability in the top fine-line metallization layer, and lower capacitance.

In another important feature of the invention, the openings 22/36/38 in polymer 20 are larger than the passivation openings 19. The polymer openings 22/36/38 are aligned with passivation openings 19. The larger polymer openings allow for relaxed design rules, simpler opening formation, and the use of a thick metal layer for the post-passivation metallization of the invention.

FIG. 2 illustrates interconnect structure 26 as well as inductor 40, wherein the inductor includes two contacts 41 and 43, through polymer layer 20 to contact pads 16.

In another feature of the invention, the FIG. 2 structure may be covered by an additional layer of polymer (not shown).

FIGS. 24 a and 24 b illustrate another feature of the invention, in which contacts to the inductor are formed in a different manner than the 2 downward contacts of FIG. 2. Specifically, in FIG. 24 a, a layer 35 of dielectric, preferably polyimide or the like, is deposited over interconnection 26 and inductor 40. An opening 36′ to one end of the inductor is then formed to expose one terminal of the inductor 40. Inductor 40 in FIG. 24 a thus can have one contact extending upward, and a second contact 40′ extending downward, in a “one-up, one-down” configuration.

FIG. 24 b illustrates another alternative, in which 2 upward contact openings 36′ and 38′ are formed from inductor 40, in a “two-up” configuration.

In both FIGS. 24 a and 24 b, the upward contacts may be used for connection to external devices or packaging, by way of wire bonding, solder bumps, or the like. For wire bonding, an upper surface of inductor 40 must be formed of a wire-bondable material such as Au or Al. For solder bump connection, under bump metallization (UBM) would be formed in the upward contact opening, followed by solder bump formation.

In either of the FIG. 24 a or 24 b configurations, interconnections to other contact pads on the same die (as opposed to connections to external devices, as described in the previous paragraph) may be made through openings 36′ and/or 38′, using similar metallization (but as an additional layer) as used for structure 26 and inductor 40.

Referring now to FIG. 24 c, another feature of the invention is shown in which extension 89, connected to inductor 40, is used to relocate an inductor contact opening 36″ to another location on the die, such as at the die edge. This may be useful for ease of wire bonding, for example. Opening 38″ is formed as earlier described. Extension 89 is formed at the same time and of the same metallization as structure 26 and inductor 40.

Similarly, extension 89 could be used to interconnect inductor 40 to another contact point on the same die, by making a downward contact (not shown, but described earlier) instead of upward contact 36″.

If a contact to a center point of the inductor, such as that shown under opening 38″ in FIG. 24 c, is desired, then such contact cannot of course be made by an extension such as 40′, but instead must be either upward or downward.

FIG. 3 shows a top view 42 of the spiral structure of the inductor 40 that has been created on the surface of layer 20 of dielectric. The inductor 40 cross section that is shown in FIG. 2 is taken along line 2-2 of FIG. 3.

FIG. 4 shows a cross section of inductor 40 whereby the inductor has been further isolated from the surface of the substrate 10 by the addition of a conductive plate 44′, of conducting material, formed under substantially all of the inductor, and preferably formed of Cu (copper) or Au (gold). The surface area of the conductive plate 44′ typically extends over the surface of passivation layer 18 such that the inductor 40 aligns with and overlays the conductive plate 44′, the surface area of conductive plate 44′ can be extended slightly beyond these boundaries to further improve shielding the surface of substrate 10 from the electromagnetic field of inductor 40.

Conductive plate 44′ can be connected to one of the inductor terminals (as shown in FIG. 4, in which it is connected to the rightmost inductor terminal 43), or may be left at a floating voltage level, or may be connected to another voltage level, deciding on the system's electrical design.

Conductive plate 44′ is formed using the methods and material of the invention, as later described with regard to the metal layer used to form metal interconnect 26 and inductor 40. Conductive plate 44′ is formed at the same time as connectors 44, which serve to connect the next level metal to contact points 16, as shown in FIG. 4.

Optionally, a second polymer layer 47 may be deposited over inductor 40 and interconnect structure 26, to provide additional protection of the metal structures.

Referring now to FIGS. 12-23, further details are provided for forming the post passivation inductor (and other passive devices) of the invention. In FIG. 12, a substrate 80 is shown, which could be an underlying dielectric layer, and a metal contact point 81, preferably comprising aluminum. A layer 84 of passivation has been patterned creating an opening 82 through layer 84 that exposes the contact pad 81. Layer 86 is a layer of polymer, preferably polyimide, as earlier described, deposited over the layer 84 of passivation, including the exposed surface of the contact pad. Polymer layer 86, such as polyimide, is typically spun on. For some thick layers of polymer, the polymer can be screen printed. Alternately, a laminated dry film polymer may be used.

FIG. 13 illustrates forming an opening 87 in polymer 86, wherein the polymer opening 87 is larger than passivation opening 82. Opening 87 is depicted having sloped sides 85. Polymer layer 86 is exposed and developed to form opening 87, which initially has vertical sidewalls. However, the subsequent curing process causes the sidewalls to have a slope 85, and a opening 87 to have a resultant partially conical shape. The sidewall slope 85 may have an angle of 45 degrees or more, and is typically between about 50 and 60 degrees. It may be possible to form the sidewalls with an angle as small as 20 degrees.

By creating relatively large vias through the layer of polyimide or polymer, aligned with smaller vias created through the underlying layer of passivation, aligned with underlying sub-micron metal layer, it is clear that the sub-micron metal vias can effectively be enlarged when progressing from the sub-micron metal layer to the level of the wide metal.

Continuing to refer to FIG. 13, one metallization system and process for forming the post passivation interconnect and inductor of the invention is depicted. First, a glue/barrier layer 88, preferably comprising TiW, is deposited, preferably by sputtering to a thickness of between about 500 and 5,000 Angstroms. A gold seed layer 90, is next sputter deposited over the glue/barrier 88, to a thickness of between about 300 and 3,000 Angstroms.

Referring now to FIG. 14, a bulk layer 92 of gold (Au) is next formed by electroplating, to a thickness of between about 1 and 20 μm. Electroplating is preceded by deposition of a thick photoresist 94 (to a thickness greater than the desired bulk metal thickness), and conventional lithography to expose the gold seed layer 90 in those areas where electroplating thick metallization is desired.

After electroplating, photoresist 94 is removed, as shown in FIG. 15. Glue/barrier Layer 88 and gold seed layer 90 are now removed, as shown in FIG. 16, by etching, using bulk Au layer 92 as a mask. One coil of inductor 40 is shown, but it would be understood that the complete inductor would be formed at the same time.

In another feature of the invention, polymer opening 87 may be only partially filled, as shown in FIGS. 17-18, which provides tight design rules for fine-pitch inductors. The design rule of polymer opening 87 is typically about 15 um, while the metal traces of inductor are as tight as a 4 um pitch. Therefore, patterning metal inside the polyimide opening is a very important feature of this technology.

Glue/barrier layer 88 and Au seed layer 90 are sputtered as previously described, and photoresist 95 formed as shown in FIG. 17, followed by electroplating gold bulk layer 92. Photoresist 95 is then stripped, and the seed layer and glue/barrier etched as previously described, and as shown in FIG. 18.

In another embodiment of the invention, copper may be used as the bulk metal in the post-passivation metallization scheme. The FIG. 13 structure is a starting point. Next, as shown in FIG. 19, a glue/barrier layer 100 of Cr or Ti is sputter deposited to a thickness of between about 200 and 2000 Angstroms. Next, a Cu seed layer 102 is sputter deposited to a thickness of between about 2,000 and 10,000 Angstroms. Bulk layer 104 of Cu is next electroplated to a thickness of between about 3 and 20 μm, also using a photoresist 94′ and conventional lithography to define the areas to be electroplated. Finally, an optional cap layer 106 comprising Ni may also be formed, also by electroplating, to a thickness of between about 0.1 and 3 um.

Referring to FIG. 20, photoresist 94′ is stripped, exposing Cu seed layer 104. Glue/barrier layer 100 and Cu seed layer 102 are now removed, as shown in FIG. 21, by etching. The bulk Cu layer 104 is used as a mask for this etch.

If optional Ni cap layer 106 is used, it acts as an etch stop during the etching of glue/barrier 100 and seed layer 102. With the Ni cap, a faster Cu etch recipe can be used for removing the seed layer since there is no loss of Cu bulk in this configuration.

One coil of inductor 40 is shown, but it would be understood that the complete inductor would be formed at the same time.

In another feature of the invention and as earlier described, polymer opening 87 may be only partially filled, as shown in FIGS. 22-23. Glue/barrier layer 100 and Cu seed layer 102 are sputtered as previously described, and photoresist 95′ formed as shown in FIG. 22, followed by electroplating Cu bulk layer 104 and Ni 106. Photoresist 95′ is then stripped, and the seed layer and glue/barrier etched as previously described, and as shown in FIG. 23.

Referring now to FIG. 5 a, layers similar to earlier descriptions are shown whereby in this case no layer of polyimide has been deposited over the layer of passivation. An inductor 19 has been created on the surface of layer 18 of passivation. The ohmic resistivity of the metal that is used for inductor 19 must be as low as possible. For this reason, the use of a thick layer of, for instance, gold is preferred for the formation of inductor 19. It has been shown that a thick layer of gold increased the Q value of inductor 19 from about 5 to about 20 for 2.4 GHz applications.

The FIG. 5 a inductor may be connected to other elements in various configurations, as earlier described. These include both terminals being connected to lower levels, as shown in FIG. 4, one up and one down as shown in FIG. 24 a, or both up as in FIG. 24 b.

An additional layer of polymer (not shown) may optionally be formed over inductor 19.

In another feature of the invention, polymer islands may be formed only under the inductor coils, and not elsewhere over the passivation layer, in order to reduce the stress caused by a larger sheet of polymer. This is depicted in FIGS. 5 b-5 c, which are a cross-sectional representation, and top view, respectively, of inductors of the invention formed on polymer islands. Each island may contain one or more than one inductor, such as on the right-most island of FIG. 5 c having a first inductor 40′ and second inductor 40′″.

Referring first to FIG. 5 b, isolated islands of polymer 20′ are formed, by depositing a polymer layer and then patterning the polymer layer to form the polymer islands. The polymer islands may also be formed by screen printing, or by dry film lamination. The islands of polymer 20′ are formed only at the location of inductors 40′ and 40″, which are formed subsequent to polymer island formation.

The inductors 40′ and 40″ of FIG. 5 b are formed as earlier described. For illustrative purposes, inductor 40″ is shown with downward contacts 41′ and 43′ connecting to metal contact points 16. Inductors 40′ are shown without contacts but could be connected upward for connection to external circuits, as described elsewhere.

FIG. 5 c is a top view of the inductors of the invention shown in FIG. 5 b, in which the FIG. 5 b cross-section is taken along line 5 b-5 b in FIG. 5 c. It can be seen in FIG. 5 c that polymer islands 20′ are isolated from one another, and polymer is only located under inductor locations—passivation layer 18 is exposed in all other areas of the substrate.

An additional protective layer of polymer (not shown) may optionally be formed over inductors 40′ and 40″.

In a similar fashion to that shown in FIGS. 5 b-5 c for inductors, polymer islands may be formed under other devices of the invention, including passive devices such as resistors and capacitors.

FIGS. 6 a-6 b depict a transformer made according to the invention. The transformer consists of bottom coil 60, and top coil 62, isolated by a dielectric layer 47. Polymer layers 20, 47 and 64 are formed, and comprise materials, previously described. Openings 66 are provided in top polymer layer 64 for connections to the top coil 62.

FIG. 6 b is a cross-sectional representation of a transformer of the invention, in which the bottom coil 60 is formed directly on passivation layer 18.

FIG. 6 c is a three-dimensional view of a solenoid structure of an inductor 19 that has been created on passivation layer 18, according to the invention. Further highlighted in FIG. 6 c are:

-   -   23, vias that are created in the thick layer of polymer 20,         having substantially vertical metal segments     -   25, the bottom metal segments of the solenoid     -   27, the top metal segments of the solenoid.         The top and bottom metal segments 25, 27 are connected, as         shown, by the substantially vertical metal segments formed in         vias 23, to form a continuous solenoid.

FIG. 6 d is a three dimensional view of a solenoid that has been created on a first layer 29 of polymer, having vias 23 created in a second layer of polymer.

FIG. 6 e is a top view of the solenoid of FIGS. 6 c and 6 d. Vias 23 are shown, connecting top metal segments 27 to bottom metal segments 25.

FIG. 6 f is a cross section of the structure of FIGS. 6 c-e, taken along line 6 f-6 f′ of FIG. 6 e.

Referring now to FIGS. 6 g-6 h, a toroidal inductor 68 is shown, also formed according to the method and structure of the invention. In FIG. 6 g, a three-dimensional view is shown, including top metal wires 27′, with vias 23′ connecting the top metal wires to the bottom metal wires 25′.

FIG. 6 h shows, for further clarification, a top view of the toroidal inductor 68 of FIG. 6 g. The highlighted features of this figure have previously been explained and therefore do not need to be further discussed at this time.

Besides inductors, it is very useful to form other passive devices, such as capacitors and resistors, using the method and structure of the invention.

FIG. 7 a is a cross section of a capacitor that has been created over a substrate 10. A layer (or layers) 14 of conductive interconnect lines and contact points 16 have been created over substrate 10. A layer 18 of passivation has been deposited over layer 14, with openings created in layer 18 of passivation through which contact pads 16 can be accessed.

A capacitor contains, as is well known, a lower plate, an upper plate and a layer of dielectric that separates the upper plate from the lower plate. FIG. 7 a includes lower plate 42, upper plate 45, and dielectric layer 46. The upper and lower plates are formed as earlier described, using electroplated Au or Cu for the bulk metals. An optional protective polymer, preferably polyimide, may be formed over the capacitor. Contacts to the capacitor may be made as described earlier for inductor terminals (both down, one up and one down, or both up).

Lower plate 42 is formed to a thickness of between about 0.5 and 20 μm. Layer 46 of dielectric is between about 500 and 50,000 Angstroms. Upper plate 45 is between about 0.5 and 20 μm thick.

The post-passivation capacitor shown in cross section in FIG. 7 a has:

-   -   reduced parasitic capacitance between the capacitor and the         underlying silicon substrate     -   allowed for the use of a thick layer of conductive material for         the capacitor plates, reducing the resistance of the capacitor;         this is particularly important for wireless applications     -   can use high-dielectric-constant material such as TiO₂ or Ta₂O₅,         in addition to polymer, Si₃N₄ or SiO₂, for the dielectric         between the upper and the lower plate of the capacitor,         resulting in a higher capacitive value of the capacitor.

The capacitor of FIG. 7 a may alternately be formed above a polymer layer (deposited over passivation 18), similar to the inductor of FIG. 4.

Dielectric layer 46 is formed of a high-K dielectric material such as Si₃N₄, TEOS, Ta₂O₅, TiO₂, SrTiO₃, or SiON, which are typically deposited by CVD (Chemical Vapor Deposition).

Alternately, the dielectric layer 46 can be a polymer film, including polyimide, benzocyclobutene (BCB), parylene or an epoxy-based material such as photoepoxy SU-8.

FIGS. 7 b-7 c show a cross section where, as in FIG. 7 a, a capacitor is created. In the cross section that is shown in FIG. 7 b a thick layer 20 of polymer has been deposited over the surface of the passivation layer 18 and has been patterned in order to make the contact pads 16 accessible though the thick layer 20 of polymer. FIG. 7 b shows the polymer vias having a smaller via diameter than the vias created through the layer of passivation. It is however preferred, as shown in FIG. 7 c, that larger vias be used in conjunction with smaller passivation vias. The thick layer 20 of polymer moves most of the capacitor, that is the lower plate 42, the upper plate 45 and the dielectric 46, further from the surface of substrate 10 by a distance equal to the thickness of layer 20. It has previously been stated that the range of polyimide thickness can vary from 2 μm to 150 μm, depending on electrical design requirements. This leads to a significant increase in distance between the capacitor and underlying structures, including metal lines and/or the silicon substrate, so that parasitic capacitance is significantly reduced.

FIGS. 7 a-7 c depict both capacitor terminals being connected down to a lower layer. The capacitor may also be contacted in one-up-one-down configuration—as shown in FIG. 25—or a two-up technique, as previously described with reference to FIG. 24 b.

Specifically relating to the cross section of FIGS. 7 a-7 c, the upper capacitor plate 45 can be connected in an upward manner through a layer of dielectric that has been deposited over the second capacitor plate 45 of FIGS. 7 a-7 c. This is further highlighted in the cross section of FIG. 25, wherein a layer 35 of dielectric has been deposited over the capacitor upper plate 45, with an opening 37 created through the layer 35 of dielectric to expose the capacitor upper plate 45, for further connection to external circuits.

The capacitor of FIGS. 7 a-7 c may optionally be covered with a protective layer of polymer, as previously described.

FIG. 8 shows a cross section of a substrate 10 over which has been deposited a layer 18 of passivation, with a resistor 48 formed over passivation layer 18. A resistor, as is well known, is created by connecting two points with a material that offers electrical resistance to the passage of current through the material. For the creation of layer 48 a resistive material is used, such as TaN, NiCr, NiSn, tungsten (W), TiW, TiN, Cr, Ti, TaSi or Ni. Among these resistive materials, NiCr provides the best TCR (Temperature Coefficient of Resistance), which can be as small as 5 ppm/° C. Resistor dimensions such as thickness, length and width of deposition of high resistive material 48 are application dependent. The resistor that is shown in cross section in FIG. 8 is, as are the capacitors of FIGS. 7 a-7 c, created in a post-passivation process on the surface of layer 18 of passivation.

FIGS. 9 a-9 b shows the resistor of the invention formed over a thick layer of polymer 20, connected to contact pads 16. By increasing the distance between the body of the resistor and the substrate (by the thickness of the polymer layer 20 and other intervening layers) the parasitic capacitance between the body of the resistor and the substrate is reduced, resulting in an improved resistive component (reduced parasitic capacitive loss, improved high frequency performance).

FIGS. 8, 9 a and 9 b show a “two-down” system for contacting the terminals of the resistor 48. The resistor may also be contacted in one-up-one-down configuration, as shown in FIG. 26, or a two-up technique, as previously described with reference to the inductor of FIG. 24 b.

An additional layer of polymer, to protect the resistor, may optionally be formed over the resistor of FIGS. 8, 9 a and 9 b.

Further applications of the post-passivation processing of the invention are shown in FIGS. 10 and 11, which concentrate on making contact points between contact pads 16 and an overlying electric component, such as a discrete inductor, capacitor, resistor or other passive device. Interconnect metal 50 of the invention is formed in polymer openings, as previously described, which are aligned with smaller passivation openings, to connect to pads 16, and serves as an under-bump metal (UBM). Solder contact bumps are formed over UBM 50 using conventional methods of selective solder deposition (plating, ball mounting, or screen printing on the surface of contacts 50), the application of a flux on the deposited solder and flowing the solder. A discrete device 54 is connected to solder balls 52 and has solder 53 to facilitate the connection. This is similar to the surface mount technology used in the assembly of printed circuit boards. The discrete electrical component may be, but is not limited to, devices such as inductors, capacitors or resistors.

FIG. 11 illustrates mounting of discrete device 54, using solder bumps 56, and UBM 50, directly over passivation layer 18.

-   -   The discrete components of FIGS. 10 and 11 have the advantages         of performance and cost savings since the discrete component         does not have to be mounted on a Printed Circuit Board as is the         common practice in the art.

UBM 50 is formed using the metallization scheme of the invention (as shown and described with respect to FIGS. 12-23), except that when Au is used as the bulk layer, its thickness is in the range of between about 0.1 and 20 μm, the thinner range being preferable to avoid a high gold concentration in the solder near the UBM/solder interface, after processing.

The invention and its various features provide the advantages of:

-   -   the discrete components provide optimized parameters and can be         mounted close to the circuits, which offer true system-on-chip         performance     -   the discrete components mounting close to the circuits also         minimizes parasitics     -   the post-passivation process of the invention allows for the         selection of discrete component design parameters that result in         reduced resistance of the discrete capacitor and the discrete         inductor, this is further clear from the following comparison         between prior art processes and the processes of the invention.         Prior approaches in the art uses thinner metal for inductors,         requiring wider coils (to minimize resistance), resulting in         increased surface area, increasing the parasitic capacitance of         the inductor and causing eddy current losses in the surface of         the substrate.

The present invention by contrast, can use easily formed thick metal layers, the thickness reducing resistance. Use of polymer 20 further separates the components formed from underlying structures, reducing capacitance. With the reduced capacitance, a higher frequency of operation results due to a higher resonant frequency.

Although the preferred embodiment of the present invention has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims. 

1. A method of fabricating a system-on-chip structure, comprising: providing a semiconductor substrate, a metallization structure over said semiconductor substrate, wherein said metallization structure comprises a first interconnect layer over said semiconductor substrate and a second interconnect layer over said first interconnect layer, a first dielectric layer between said first and second interconnect layers, and a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises an oxide layer and a nitride layer; forming a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than a thickness of said passivation layer; and forming a capacitor over said first polymer layer, wherein said capacitor comprises a lower plate on said first polymer layer, an upper plate over said lower plate, and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 Angstroms, wherein forming said lower plate comprises depositing a first metal layer, followed by depositing a second metal layer over said first metal layer, followed by forming a first photoresist layer over said second metal layer, wherein a first opening in said first photoresist layer is over said second metal layer and exposes said second metal layer, followed by electroplating a third metal layer over said second metal layer exposed by said first opening, followed by removing said first photoresist layer, followed by removing said second metal layer not under said third metal layer, followed by removing said first metal layer not under said third metal layer, and wherein forming said upper plate comprises depositing a fourth metal layer, followed by depositing a fifth metal layer over said fourth metal layer, followed by forming a second photoresist layer over said fifth metal layer, wherein a second opening in said second photoresist layer is over said fifth metal layer and exposes said fifth metal layer, followed by electroplating a sixth metal layer over said fifth metal layer exposed by said second opening, followed by removing said second photoresist layer, followed by removing said fifth metal layer not under said sixth metal layer, followed by removing said fourth metal layer not under said sixth metal layer.
 2. The method of claim 1, wherein said forming said first polymer layer comprises a coating process.
 3. The method of claim 1, wherein said first polymer layer comprises polyimide.
 4. The method of claim 1, wherein said first polymer layer comprises benzocyclobutene (BCB).
 5. The method of claim 1, wherein said forming said first polymer layer comprises a curing process.
 6. The method of claim 1, wherein said depositing said fourth metal layer comprises sputtering a titanium-containing layer having a thickness between 500 and 5,000 Angstroms.
 7. The method of claim 1, wherein said depositing said fifth metal layer comprises sputtering a gold layer on said fourth metal layer, wherein said gold layer has a thickness between 300 and 3,000 Angstroms.
 8. The method of claim 1, wherein said depositing said fifth metal layer comprises sputtering a copper layer on said fourth metal layer, wherein said copper layer has a thickness between 2,000 and 10,000 Angstroms.
 9. The method of claim 1, wherein said depositing said first metal layer comprises sputtering a titanium-containing layer having a thickness between 500 and 5,000 Angstroms.
 10. The method of claim 1, wherein said depositing said second metal layer comprises sputtering a gold layer on said first metal layer, wherein said gold layer has a thickness between 300 and 3,000 Angstroms.
 11. The method of claim 1, wherein said depositing said second metal layer comprises sputtering a copper layer on said first metal layer, wherein said copper layer has a thickness between 2,000 and 10,000 Angstroms.
 12. The method of claim 1, wherein said electroplating said sixth metal layer comprises electroplating a gold layer on said fifth metal layer exposed by said second opening, wherein said gold layer has a thickness between 1 and 20 micrometers.
 13. The method of claim 1, wherein said electroplating said third metal layer comprises electroplating a gold layer on said second metal layer exposed by said first opening, wherein said gold layer has a thickness between 1 and 20 micrometers.
 14. The method of claim 1, wherein said electroplating said third metal layer comprises electroplating a copper layer on said second metal layer exposed by said first opening, wherein said copper layer has a thickness between 3 and 20 micrometers.
 15. The method of claim 1, wherein said electroplating said sixth metal layer comprises electroplating a copper layer on said fifth metal layer exposed by said second opening, wherein said copper layer has a thickness between 3 and 20 micrometers.
 16. The method of claim 1, wherein said forming said lower plate further comprises, after said electroplating said third metal layer, electroplating a seventh metal layer on said third metal layer in said first opening, followed by said removing said first photoresist layer.
 17. The method of claim 16, wherein said electroplating said seventh metal layer comprises electroplating a nickel layer on said third metal layer in said first opening, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.
 18. The method of claim 1, wherein said forming said upper plate further comprises, after said electroplating said sixth metal layer, electroplating a seventh metal layer on said sixth metal layer in said second opening, followed by said removing said second photoresist layer.
 19. The method of claim 18, wherein said electroplating said seventh metal layer comprises electroplating a nickel layer on said sixth metal layer in said second opening, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.
 20. The method of claim 1, wherein said depositing said first metal layer comprises sputtering a titanium-tungsten-alloy layer having a thickness between 500 and 5,000 Angstroms.
 21. The method of claim 1, wherein said depositing said fourth metal layer comprises sputtering a titanium-tungsten-alloy layer having a thickness between 500 and 5,000 Angstroms.
 22. The method of claim 1 further comprising forming a second polymer layer over said capacitor.
 23. The method of claim 1, wherein said second dielectric layer comprises SrTiO₃.
 24. The method of claim 1, wherein said second dielectric layer comprises TEOS.
 25. The method of claim 1, wherein said second dielectric layer comprises SiON.
 26. The method of claim 1, wherein said second dielectric layer comprises Si₃N₄.
 27. The method of claim 1, wherein said second dielectric layer comprises SiO₂.
 28. A method of forming a system-on-chip structure, comprising: providing a semiconductor substrate, a metallization structure over said semiconductor substrate, wherein said metallization structure comprises a first interconnect layer over said semiconductor substrate and a second interconnect layer over said first interconnect layer, a first dielectric layer between said first and second interconnect layers, and a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises an oxide layer and a nitride layer; and forming a capacitor over said passivation layer, wherein said capacitor comprises a lower plate over said passivation layer, an upper plate over said lower plate, and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 Angstroms, wherein forming said lower plate comprises depositing a first metal layer, followed by depositing a second metal layer over said first metal layer, followed by forming a first photoresist layer over said second metal layer, wherein a first opening in said first photoresist layer is over said second metal layer and exposes said second metal layer, followed by electroplating a third metal layer over said second metal layer exposed by said first opening, followed by removing said first photoresist layer, followed by removing said second metal layer not under said third metal layer, followed by removing said first metal layer not under said third metal layer, and wherein forming said upper plate comprises depositing a fourth metal layer, followed by depositing a fifth metal layer over said fourth metal layer, followed by forming a second photoresist layer over said fifth metal layer, wherein a second opening in said second photoresist layer is over said fifth metal layer and exposes said fifth metal layer, followed by electroplating a sixth metal layer over said fifth metal layer exposed by said second opening, followed by removing said second photoresist layer, followed by removing said fifth metal layer not under said sixth metal layer, followed by removing said fourth metal layer not under said sixth metal layer.
 29. The method of claim 28, wherein said depositing said first metal layer comprises sputtering a titanium-containing layer having a thickness between 500 and 5,000 Angstroms.
 30. The method of claim 28, wherein said depositing said second metal layer comprises sputtering a gold layer on said first metal layer, wherein said gold layer has a thickness between 300 and 3,000 Angstroms.
 31. The method of claim 28, wherein said depositing said second metal layer comprises sputtering a copper layer on said first metal layer, wherein said copper layer has a thickness between 2,000 and 10,000 Angstroms.
 32. The method of claim 28, wherein said electroplating said third metal layer comprises electroplating a gold layer on said second metal layer exposed by said first opening, wherein said gold layer has a thickness between 1 and 20 micrometers.
 33. The method of claim 28, wherein said electroplating said third metal layer comprises electroplating a copper layer on said second metal layer exposed by said first opening, wherein said copper layer has a thickness between 3 and 20 micrometers.
 34. The method of claim 28, wherein said forming said lower plate further comprises, after said electroplating said third metal layer, electroplating a seventh metal layer on said third metal layer in said first opening, followed by said removing said first photoresist layer.
 35. The method of claim 34, wherein said electroplating said seventh metal layer comprises electroplating a nickel layer on said third metal layer in said first opening, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.
 36. The method of claim 28, wherein said depositing said first metal layer comprises sputtering a titanium-tungsten-alloy layer having a thickness between 500 and 5,000 Angstroms.
 37. The method of claim 28, wherein said depositing said fourth metal layer comprises sputtering a titanium-containing layer having a thickness between 500 and 5,000 Angstroms.
 38. The method of claim 28, wherein said depositing said fifth metal layer comprises sputtering a gold layer on said fourth metal layer, wherein said gold layer has a thickness between 300 and 3,000 Angstroms.
 39. The method of claim 28, wherein said depositing said fifth metal layer comprises sputtering a copper layer on said fourth metal layer, wherein said copper layer has a thickness between 2,000 and 10,000 Angstroms.
 40. The method of claim 28, wherein said electroplating said sixth metal layer comprises electroplating a gold layer on said fifth metal layer exposed by said second opening, wherein said gold layer has a thickness between 1 and 20 micrometers.
 41. The method of claim 28, wherein said electroplating said sixth metal layer comprises electroplating a copper layer on said fifth metal layer exposed by said second opening, wherein said copper layer has a thickness between 3 and 20 micrometers.
 42. The method of claim 28, wherein said forming said upper plate further comprises, after said electroplating said sixth metal layer, electroplating a seventh metal layer on said sixth metal layer in said second opening, followed by said removing said second photoresist layer.
 43. The method of claim 42, wherein said electroplating said seventh metal layer comprises electroplating a nickel layer on said sixth metal layer in said second opening, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.
 44. The method of claim 28, wherein said depositing said fourth metal layer comprises sputtering a titanium-tungsten-alloy layer having a thickness between 500 and 5,000 Angstroms.
 45. The method of claim 28, wherein said second dielectric layer comprises SrTiO₃.
 46. The method of claim 28, wherein said second dielectric layer comprises TEOS.
 47. The method of claim 28, wherein said second dielectric layer comprises SiON.
 48. The method of claim 28, wherein said second dielectric layer comprises Si₃N₄.
 49. The method of claim 28, wherein said second dielectric layer comprises SiO₂.
 50. The method of claim 28 further comprising forming a polymer layer on said passivation layer, followed by said forming said capacitor on said polymer layer.
 51. The method of claim 50, wherein said polymer layer comprises polyimide.
 52. The method of claim 28 further comprising forming a polymer layer over said capacitor.
 53. The method of claims 52, wherein said polymer layer comprises polyimide. 